Smartphone Futurology: The science behind your next phone's processor and memory
Welcome to Smartphone Futurology. In this new series of science-filled articles, Mobile Nations guest contributor Shen Ye walks through current technologies in use within our phones, as well as the cutting-edge stuff still being developed in the lab. There's quite a bit of science ahead, as a lot of the future discussions are based on scientific papers with a vast amount of technical jargon, but we've tried to keep things as plain and simple as possible. So if you want to dive deeper into just how the guts of your phone function, this is the series for you.
A new year brings the certainty of new devices to play with, and so it's time to look ahead at what we might see in the smartphones of the future. The first instalment in the series covered what's new in battery tech, while the second article looked at what's next in the world of mobile displays. The series' third part focuses on the electronic brains of our mobile devices — the SoC (system on a chip) and flash storage. The rise of smartphones, and fierce competition among rival manufacturers, has accelerated the pace of technological progress in both these areas. And we're not done yet — there are ever wilder technologies on the horizon that may some day find their way into future devices. Read on to find out more.
About the author
Shen Ye is an Android developer and MSci graduate in Chemistry from the University of Bristol. Catch him on Twitter @shen and Google+ +ShenYe.
More in this series
Be sure to check out the first two instalments of our Smartphone Futurology series, covering the future of battery technology and smartphone display tech. Keep watching for more in the coming weeks.
The smartphone industry has immensely accelerated advancements in microchip technology, in both processors and flash memory. The HTC G1 from 6 years ago had a 528 MHz processor made using a 65 nanometer process, and a 192MB RAM module. We've come a long way since then, with Qualcomm releasing 64 bit processors this year using a 20 nm process. In this instalment of Smartphone Futurology, we'll look at future technologies in both storage and processing power, along with challenges to be overcome if we want to continue to accelerate at this pace.
Smartphones utilize an integrated circuit known as an SoC (system on a chip). This bundles multiple components needed for the device to function all in a single chip, including connectivity radios, CPU, GPU, multimedia decoders, etc. When phone manufacturers decide on the SoC they want to use, they can select the package variant they would like, each with a different CPU clock speed and size. For example, both the Nexus 7 (2012) and HTC One X used a Tegra 3 chipset, but despite the identical branding, the SoC layout, speed and size are different.
Larger packages such as quad flat packages tend to be the cheapest, while smaller ones such as ball mounts are more expensive as they require more costly processes to achieve their size. The 2014 flagships such as the M8 and S5 had the SoC layered beneath the RAM to save space. However, these components operate very similarly to that of a normal PC, all powered by microchips filled with unimaginably small transistors.
Transistors are tiny semiconductor devices that can be used as switches or amplifiers. The number of transistors in a processor tends to determine its processing power. The nanometer manufacturing process term defines the size of the processor. With 20nm transistors, you can fit around 250 billion of them on a silicon wafer around the size of a fingernail.
Above is a simple diagram of a transistor. The silicon is a semiconductor which in its normal state is insulating. When a weak signal is introduced to the control gate, it can reach a threshold where it "dopes" the region of semiconductor it is placed above with an electric field, causing it to conduct electricity and thus completing a connection between the source and drain. To close off the circuit, the control gate is simply switched off. Transistors are made using a long series of chemical etching and deposition processes, but their manufacturing costs are continuously plummeting as new techniques and optimizations are discovered.
Apple has increasingly been taking over the design of their mobile chipsets. The A8X that ships inside the iPad Air 2 has a custom tri-core ARM CPU and custom octa-core PowerFX GPU, for a total of 3 billion transistors on-die.
NAND Flash Memory
The majority of phones use NAND flash memory storage, a non-volatile type of storage – more specifically EEPROM (Electrically Erasable Programmable Read Only Memory). Contrary to what the name suggests, the Read Only Memory (ROM) isn't actually read-only, though the read speeds are definitely faster than write speeds. The name "NAND flash" is from the NAND logic gate (NOT AND or Negated AND), which produces a "false" output if the input is "true", used in the transistors that make up the NAND flash storage.
Above is an illustration of a floating gate transistor which stores information. It's just a transistor with a floating gate electrically insulated with an oxide layer and has no electrical contacts. The floating gate is able to hold a negative charge, and this is what is used to store information. The insulation allows it to maintain the charge for a very long time. In single-level cell (SLC) flash each floating gate has 2 states where it is either negatively charge or has no charge, thus can store 1 bit. In multi-level cell (MLC) flash each floating gate can have multiple states depending on how negatively charged it is. MLC flash allows denser storage media compared to SLC flash but it has a higher rates of read/write error due to the narrower differences between states.
When reading the state of a floating gate, it uses a similar mechanism to how a normal transistor works. A voltage is applied on the control gate to reach the threshold where the connection between the source and drain can be complete. The voltage required is proportional to how negatively charged the floating gate is. The bit value of the transistor is translated from the voltage required for the transistor to switch on. When writing, the circuitry has to somehow modify the charge of the floating gate when it's completely insulated from any other electrical components. It requires a phenomenon called "quantum tunnelling" – where a particle (an electron in this case) can tunnel through a barrier. This writing process is significantly more complicated and slower than the reading process, thus read speeds are always higher than write speeds.
Charge trap flash (CFT) is also used instead of floating gate transistors, the mechanism is almost identical except CFT transistors use a thin film to store the negative charge instead of a floating gate. Their advantage over floating gate is that they're more reliable, cheaper to manufacture due to fewer processes, and they are smaller so they have a denser capacity. This is seen as the future of NAND as floating gate transistors are extremely difficult to manufacture below 20 nm. However, with transistors approaching sub-20nm sizes this can mean unviable error rates and low data retention times (i.e. your device may become corrupt if you leave it unpowered for extended periods of time). With floating gate transistors, sizes lower than 20nm can increase charge interference between floating gates – thus significantly increasing error and corruption rates.
3D NAND (sometimes known as Vertical NAND or V-NAND) only recently became available to the mass market, with the Samsung 850 series SSDs using them. 3D NAND flash provides faster performance with improved longevity and reliability. Originally announced by Samsung Electronics last year, they were able to scale NAND technology vertically as opposed to the aggressive horizontal scaling in the current market. Samsung discovered a method of altering the shape of each transistor into a cylindrical form and stacking layers of these cylindrical transistors to maximize their NAND flash storage density per area.
3D NAND flash brings lower cost per GB, bringing it closer to that of magnetic storage (like traditional mechanical hard drives). Additionally it helps solve current problems with downscaling transistor sizes below 20 nm, including reduction in interference between transistors.
Phase Change Flash
In the last article of the series, we discussed phase change crystal IGZO displays which Sharp recently demoed in their Aquos devices. Instead of states with difference charges, phase change materials (PCM) change their structure between crystalline (ordered) and amorphous (disordered). With silicon vendors competing to find a new technology to replace NAND flash due to sub-20nm scaling issues, phase change flash is emerging as a strong candidate.
This year both IBM and Western Digital demonstrated their efforts in creating PCM SSDs. Compared to current NAND memory, phase change memory has considerably lower latency — down from 70 microseconds to a single microsecond. Unlike how NAND uses charges, PCM would not have interference with another transistor at sub-20nm scales as long as they are isolated.
The currently preferred PCM is a chalcogenide alloy1. Using a tiny resistor (heater) placed beneath each section of chalcogenide, the phase of the material can be changed just by adjusting the temperature and time of a pulse of heat from the resistor. Each resistor has to be wrapped in a thermal insulator to prevent "thermal cross-talk", when the heat from a resistor affects other "bits" of PCM. The time scales we're talking about are in the 10-30 nanosecond region, so extremely fast writing speeds. The reading process is just as fast, with the crystalline phase being a better conductor, thus reading the bit value is as simple as passing a small current through the PCM and measuring its resistance. The results have been very promising and we should expect phase change flash memory to be adopted over current NAND technologies within the next decade.
Non-volatile Magnetic RAM (MRAM)
Magnetism was proposed as a way of storing data over a decade ago but methods for manufacturing have only recently been demonstrated2. This next-generation technology is still far away, but has now moved from pen and paper to production. The latency of MRAM is also vastly lower than that of current NAND chips, in the low tens of nanoseconds.
Everspin has partnered with Global Foundries to product spin torque magnetic RAM (ST-MRAM) using a 40nm process. TDK also showed off its ST-MRAM technology, though only at 8Mbit compared to the 64Mbit of Everspin. The two companies are in a race to mature their MRAM technologies for the consumer market.
Moving onto RAM, most current flagship devices use LPDDR3 mobile RAM (LP stand for Low Power). Its adoption in the market was rapid, with JEDEC only publishing the LPDDR3 standard in May 2012. Earlier in August, they published the LPDDR4 standard with Samsung electronics' first 20nm class LPDDR4 chip capable of reaching data rates of 3200 Mbit/s, 50% higher than that the previous generation and uses a 10% lower voltage, thus an overall 40% increase in power efficiency.
With 2K screens already in our mobile devices and 4K round the corner for tablets, our appetite for RAM continues to grow. RAM is volatile – it requires a constant voltage to maintain its stored data, so power consumption is just as important as speed. We'll most likely be seeing LPDDR4 chips in our flagship phones and tablets in 2015 and we'll be another step closer to never having to worry about background apps bogging down the entire device.
Sub-20nm microchip fabrication
Silicon vendors like Qualcomm and Intel are constantly looking for ways to squeeze more transistors onto a processor to ultimately increase their performance. We mentioned above how NAND transistors have issues with data storage below 20nm, not to mention the vast decrease in product yields. Another problem currently being heavily researched is the issue with transferring sub-20nm designs to the silicon wafer.
Current techniques use light to project the design onto a silicon wafer with light sensitive material – imagine using a projector to display an image at the nanometer scale. When you dip below 20nm you hit a few difficulties with this lithography process, limited by the laws of physics. When you get to such small scales, the diffraction of light begins to become an issue.
As you may know, light travels as a wave. If the wave passes through a gap (the silicon design template in this case) whose size is close to the light's wavelength, it can diffract and give a very blurred transfer. So surely we can just increase the wavelength of light, right? Well that only fixes the issues temporarily until you want to go even smaller, additionally you would need to find a new light sensitive material which would react to the new wavelength of light. This is exactly what's happening right now, with "extreme ultraviolet lithography" (EUV) being the next generation of lithography techniques, able to push the 20nm limit down to 13.5nm.
Silicon vendors have already looked into how to break the next brick wall they will inevitably face, 13.5nm. One highly researched area in this field is on self-assembling nanowires. These are long polymer chains which have been designed to organize themselves into specific patterns. A group at the University of Toronto published a paper3 on how they got a solution of their polymer chains to organize themselves into thin, evenly spaced lines that could actually conduct electricity.
Image credit: D-Wave
Quantum computing and Qubits
Quantum computing is still in its infancy but many believe it's the future of computing. It's incredibly complex, so we're going to just lay out the basics here. A lot of what happens at the quantum level is really weird compared to what we see daily; 4 years after doing a science degree I still sometimes have issues grasping certain parts of quantum mechanics.
Conventional computers use bits, which can only be one of two states, either 1 or 0. A qubit (quantum bit) can be in multiple states at the same time, and thus is able to process and store large amounts of data. This is due to a quantum phenomenon known as superposition, the basis of how quantum computing works (this is commonly explained with the Schrodinger's cat analogy).
Another phenomenon known as "entanglement" can happen at the quantum level, where a pair of particles interact in such a way that they can't be described on their own but as a whole. This causes weird things to happen such as changing the state of one of the particles and somehow the other particle will instantaneously change as well, despite them being far apart with no physical link in between. The issue with a qubit is that if you try to read it directly, you'd have to interact with it in some way which would change its value. However, quantum entanglement potentially solves the problem. If you entangle the qubit, you can measure its pair which allows researchers to read the value of qubit without actually looking at it.
Last year Google announced that they were launching an A.I. lab with a 512-qubit quantum computer, though currently it requires a huge room full of tools to help keep it at the optimal condition to run. But that's also how the conventional computer started off as well. It will be well over 2 decades before we get it in our phones, but it is most definitely a heavily researched area that's continuously growing.
The bottom line
The silicon market is so competitive at the moment that new discoveries and standards are being adopted rapidly into the market. We'll have 3D NAND and LPDDR4 coming very soon to our devices, bringing considerably faster performance and better power efficiency. We discussed a few areas of research being generously funded to help silicon vendors get an edge in the aggressive market – though competition in the tech industry has always ended up massively benefiting the consumer.
- R. Bez. Chalcogenide PCM: a memory technology for next decade. in Electron Devices Meeting (IEDM), 2009 IEEE International. 2009. ↩
- L. Liu, C.-F. Pai, Y. Li, H.W. Tseng, D.C. Ralph, and R.A. Buhrman, Spin-Torque Switching with the Giant Spin Hall Effect of Tantalum, Science, 2012. 336(6081): p. 555-558. ↩
- H. Wang, M.A. Winnik, and I. Manners, Synthesis and Self-Assembly of Poly(ferrocenyldimethylsilane-b-2-vinylpyridine) Diblock Copolymers, Macromolecules, 2007. 40(10): p. 3784-3789. ↩
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